Parity
You may have heard the term parity when shopping for computer memory:
Parity requires an additional bit added to the system: this bit is set to 0 or 1 to make the number of 1's even (even parity) or odd (odd parity). This is used to detect errors in data transmission: for example,
in a system with even parity, the following data is received:
110101101
000000000
101010100
110000001
101110011
... the last bit is the parity bit: This data is 8 bits long, plus one parity bit - 9 bits. Look again, this time with the parity bit highlighted:
----data---- = number of 1's in the data
110101101 ... = 6
000000000 ... = 0
101010100 ... = 4
110000001 ... = 3
101110011
... = 6
Look closely at the data: the 3rd item has an odd number of 1's. If this system used even parity, this would mean there is an error in that string of 0's and 1's. We don't know where the error is: in fact, it may be in the parity bit itself, but we know there is an error.
Parity Detector and Parity Checker
We can build two circuits to accomplish a function: using XOR gates, we can build a parity generator.
If we have a 4-bit number and we want to send it to another board, we could just send the number:
But, what if errors occassionally occurred? We could add the capability to detect an error by adding a parity bit. We'll design the system for even parity:
This design requires additional gates (if we are using a programmable
device, this should easily be contained in the device: if we are using
chips, this would cost us one additional chip). The advantage is that
we can detect an error.
See yout text (figure 6-11) for the design of a parity checker: this would be built on board 2 in our example.
Thought provoking question: What if we had 2 lines with an error? Answer: it would show up as valid data. Therefore, this circuit detects one bit in error, but not two. Of course, we hope the odds of two bits in error are very low... |
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